CSU-Carig
Turbo decoder architecture for beyond-4G applications /
by Wong, Cheng-Chi,
| Item type | Location | Collection | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|---|
Electronic Books
|
E-Resource Section | E-Books | 621.3981 (Browse shelf) | Available |
Browsing Cagayan State University - Carig Library Shelves , Shelving location: E-Resource Section , Collection code: E-Books Close shelf browser
Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture.
This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques--
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